Many structures are required during the manufacture of a semiconductor device, such as conductive plugs, transistors, capacitors, and conductive lines. A common design goal of semiconductor engineers is to decrease the size of these features to increase the number of features which can be formed in a given area. Decreasing feature size results in decreased production costs and, ultimately, miniaturized electronic devices into which the semiconductor device is installed.
Increasing electrical interference between adjacent features is a concern with decreasing device feature size. For example, as the width of conductive lines and the spacing between adjacent lines decreases, electrical crosstalk and resistance-capacitance (RC) delay increases. Copper interconnections with low-k interlayer dielectric (ILD) materials have been introduced for advanced integrated circuits (IC's) to reduce the RC delay of interconnections. Properties of ILD's and their fabrication techniques used with circuit miniaturization, for example using fine copper interconnects, must provide various properties such as a low dielectric constant (low-k) and electrical properties such as high bulk resistivity and breakdown field strength. They must also have good mechanical properties, such as resistance to separation from the copper interconnect during thermal changes and good chemical properties such as being chemically inert and stable. Further, they must accept planarization, have narrow gap filling capability, and have a low processing temperature to conserve the thermal budget.
One method currently used to form ILD's comprises doping silicon dioxide with fluorine which results in an SiO2F layer having a decreased dielectric constant. However, present processing technologies are not able to deliver high quality films of SiO2F for low-k ILD, and these films typically suffer from relatively high dielectric constants of about 3.6. Chemical vapor deposition (CVD) processes are limited by thermodynamic constraints and, consequently, the reduction in the dielectric constant is relatively small. It is difficult to reduce the dielectric constant of fluorinated SiO2 films to below 3.5, because the electrical and mechanical properties of SiO2F dielectric films, such as bulk resistivity and breakdown field strength, are usually degraded. Also, there are reliability concerns with the addition of fluorine which result from chemical interaction of the fluorine with the metal interconnect which the SiO2F ILD contacts. Fluorine species in SiO2F films are not stable and easily absorb moisture to form OH and HF radicals. The existing OH will increase the dielectric constant of the ILD, and both HF and OH radicals can corrode dielectrics and metal layers.
To overcome the thermodynamic and reliability problems of SiO2F films formed using CVD, ion implantation, particularly multi-species implantation by plasma immersion ion implantation (PIII), can be used to fabricate fluorinated SiO2 ILD's. However, PIII fluorinated SiO2 films have a minimum dielectric constant of about 2.8. Further, this technique is relatively new and films formed using this process need to be more thoroughly investigated for stability.
Porous dielectric materials have also been developed to reduce the dielectric constant and overcome problems with prior films. Dielectric constants as low as about 2.6 have been claimed by these dielectrics. Various challenges are associated with this class of materials for use with integrated circuits. For example, most low-k porous dielectric processes involve the use of either organic or inorganic materials which require a relatively high temperature for the decomposition and chemical reaction which uses a significant portion of the thermal budget. These materials may also suffer from poor mechanical, chemical, and thermal stability due to their lower density and the porous structure itself, and thus the reliability of the porous films is questionable. With decreasing dielectric constants the stability and reliability of the porous film also decreases. A barrier layer may be required between a copper interconnect and a porous ILD layer to protect the dielectric from copper diffusion and from process gasses and other chemical penetrations. A thin film which is formed on a porous ILD can also become porous from absorption of the then film into the porous ILD. Thus sealing of the pores of porous ILD's is required. Barrier layers of silicon carbide (SiC), titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN) formed by atomic layer deposition (ALD) have been proposed due to the good barrier capability and highly conformal result on the porous ILD. While a k-value as low as about 2.6 has been claimed by porous ILD's, it is difficult to achieve this result reliably with a reliable, stable film.
Generally, porous ILD's suffer from various problems. It is difficult to use porous ILD's with interconnects such as copper, because during surface planarization the porous ILD continues to etch at a high rate once the copper interconnect is exposed, thereby resulting in an uneven surface. Porous ILD's also have poor mechanical strength due to its lower density and porous structure. Moisture absorption of the porous film is also a concern due to the large porous surface area, and it is difficult to reliably seal the porous film with a barrier which will not itself be absorbed into the film. New materials and processes must be developed before porous ILD layers can be successful.
A method for forming a dielectric layer, and a structure resulting from the inventive method, which allows for a multilayer interconnect while reducing or eliminating the problems with prior films as described above would be desirable.